Cascode architecture is an efficient and cost effective design technique to overcome the reliability issues regarding Gate-Oxide breakdown. This method is employed for circuits such as DC-DC converters and power amplifiers operating with input supply voltage higher than transistor breakdown voltage. Design of the gate bias circuit which controls the switching operation of the power stage transistors is the main challenge in this technique, especially for the power stage with more than two stacked transistors. The bias circuit generates the required gate drive signals with proper timing to avoid the voltage stress condition.

This thesis presents design and simulation results of the buck type DC-DC converter based on 45nm CMOS technology. Breakdown voltage of the transistor is 1.1V. Therefore, 6-stacked power stage configuration is proposed for a fixed input voltage of 6V by considering a maximum supply voltage of 1V for each transistor. Switching operation of the power stage is controlled by driving signals for PMOS and NMOS stacked tran-sistors. In order to generate the driver signal, three cascade stages of high speed level shifters are employed to shift up the driver signal by 5V. Switching frequency is 52MHz and open loop control scheme is considered for the buck converter. The control circuit consists of a Schmitt trigger and a Non-Overlapping switching circuit to gener-ate the driving signals with adjusted dead times. The designed buck converter provides an output voltage of 1.25V and has an efficiency of 79.2% with a fixed input power of 207mW. A second buck converter circuit is also presented that operates under variable battery voltages from 3.5V to 6V. Using the designed circuit the output voltage is 1.25V and a maximum power conversion efficiency of 81.3% is obtained for an input voltage of 3.9V. The output power is 200mW and a high power density of 195mW/mm3 is achieved